• The MASE project at University of Michigan, under the direction of Prof. Todd Austin, provides microarchitectural modeling infrastructure for SimpleScalar developers.
• The PowerAnalyzer project at University of Michigan, under the direction of Profs. Trevor Mudge, Todd Austin, and Dirk Grunwald, is building power analysis tools based on the SimpleScalar simulators.  The PowerAnalyzer project, along with SimpleScalar LLC, also develops the SimpleScalar/ARM target.
• The SIMCA project at University of Minnesota, from Prof. Lilja's ARCTiC Lab, is an execution driven simulator that simulates the hardware component interactions in the Superthreaded Architecture computer processor.
• The Wattch project at Princeton University, under the direction of Prof. Margaret Martonosi, is developing power analysis tools based on SimpleScalar simulators.
• The HydraScalar project at the University of Virginia, under the direction of Prof. Kevin Skadron, has developed SimpleScalar-based simulators to support aggressive speculation techniques such as multipath execution.

In addition, the SimpleScalar tools are used widely for computer architecture research and instruction.  For example, in the year 2002, more than one third of all papers published in top computer architecture conferences used the SimpleScalar tools to evaluate their designs.  Here are a few recent research papers that have used SimpleScalar tools to evaluate their designs:

2003

W. Zhang, M. Kandemir, A. Sivasubramanian, and M.J. Irwin (Pennsylvania State University), Performance, Energy, and Reliability Tradeoffs in Replicating Hot Cache Lines, in the 2003 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2003), October 2003.

Dinesh Suresh, Banit Agrawal, Jun Yang, Walid Najjar, and Laxmi Bhuyan (University of California, Riverside), Power Efficient Encoding Techniques for Off-chip Data Buses, in the 2003 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2003), October 2003.

Rajeev Krishna, Scott Mahlke, and Todd Austin (University of Michigan), Architectural Optimizations for Low-Power, Real-Time Speech Recognition, in the 2003 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2003), October 2003.

Binu Mathew, Al Davis, and Zhen Fang (University of Utah), A Low­Power Accelerator for the SPHINX 3 Speech Recognition System, in the 2003 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2003), October 2003.

Ann Gordon-Ross and Frank Vahid (University of California, Riverside), Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware, in the 2003 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2003), October 2003.

Jeremy Lau, Stefan Schoenmackers (University of California, San Diego), Timothy Sherwood (University of California, Santa Barbara), and Brad Calder (University of California, San Diego), Reducing Code Size With Echo Instructions, in the 2003 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2003), October 2003.

Youtao Zhang (University of Texas at Dallas) and Rajiv Gupta (University of Arizona), Enabling Partial Cache Line Prefetching Through Data Compression, in the 2003 International Conference on Parallel Processing (ICPP-2003), October 2003.

Magnus Ekman and Per Stenstrom (Chalmers University of Technology), Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores, in the 2003 International Conference on Parallel Processing (ICPP-2003), October 2003.

Santithorn Bunchua, D. Scott Wills, and Linda M. Wills (Georgia Institute of Technology), Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Sudeep Pasricha and Alex Veidenbaum (University of California, Irvine), Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, and Doug Burger (University of Texas at Austin), Exploiting Microarchitectural Redundancy For Defect Tolerance, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Kaushal R. Gandhi and Nihar R. Mahapatra (Michigan State University), A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Peter Petrov and Alex Orailoglu (University of California at San Diego), Virtual Page Tag Reduction for Low-power TLBs, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, and Kanad Ghose (State University of New York, Binghamton), Distributed Reorder Buffer Schemes for Low Power, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Sriram Nadathur and Akhilesh Tyagi (Iowa State University), A Dependence Driven Efficient Dispatch Scheme, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Nihar R. Mahapatra (Michigan State University), Jiangjiang Liu (University at Buffalo, SUNY), and Krishnan Sundaresan (Michigan State University), Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Sobeeh Almukhaizim, Thomas Verdel and Yiorgos Makris (Yale University), Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Jaume Abella and Antonio Gonzalez (Universitat Politecnica de Catalunya), On Reducing Register Pressure and Energy in Multiple-Banked Register Files, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Jaume Abella and Antonio Gonzalez (Universitat Politecnica de Catalunya), Power Efficient Data Cache Designs, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Aneesh Aggarwal and Manoj Franklin (University of Maryland), Energy Efficient Asymmetrically Ported Register Files, in the 2003 International Conference on Computer Design (ICCD-2003), October 2003.

Adam Wiggins, Simon Winwood, Harvey Tuch, and Gernot Heiser (University of New South Wales), Legba: Fast Hardware Support for Fine-Grained Protection, in the 2003 Asia-Pacific Computer Systems Architecture Conference (ACSAC-2003), September 2003.

Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, and Kanad Ghose (State University of New York, Binghamton), Reducing Datapath Energy Through the Isolation of Short–Lived Operands, in the 2003 International Conference on Parallel Architectures and Compilation Techniques (PACT-2003), September 2003.

Erez Perelman, Greg Hamerly, and Brad Calder (University of California, San Diego), Picking Statistically Valid and Early Simulation Points, in the 2003 International Conference on Parallel Architectures and Compilation Techniques (PACT-2003), September 2003.

Yutao Zhong, Steven G. Dropsho, and Chen Ding (University of Rochester), Miss Rate Prediction across All Program Inputs, in the 2003 International Conference on Parallel Architectures and Compilation Techniques (PACT-2003), September 2003.

Nicholas Wang, Michael Fertig, and Sanjay Patel (University of Illinois at Urbana-Champaign), Y-Branches: When You Come to a Fork in the Road, Take It, in the 2003 International Conference on Parallel Architectures and Compilation Techniques (PACT-2003), September 2003.

Aneesh Aggarwal and Manoj Franklin (University of Maryland, College Park), Instruction Replication: Reducing Delays due to Inter-PE Communication Latency, in the 2003 International Conference on Parallel Architectures and Compilation Techniques (PACT-2003), September 2003.

Akihiro Chiyonobu and Toshinori Sato (Kyushu Institute of Technology), On Identifying Instruction Criticality for Energy-Aware Applications, in the PACT 2003 Work in Progress Session, September 2003.

Akihito Sakanaka and Toshinori Sato (U. Fukuoka, Japan), Reducing Static Energy of Cache Memories via Prediction-Table-less Way Prediction, in the 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS-2003), September 2003.

Amirali Baniasadi (University of Victoria, Canada), Power-Aware Branch Predictor Update for High-Performance Processors, in the 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS-2003), September 2003.

Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, and Kanad Ghose (State University of New York, Binghamton), Energy Efficient Register Renaming, in the 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS-2003), September 2003.

Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, and Kaushik Roy (Purdue University), A Forward Body-Biased Low-Leakage SRAM Cache: Device and Architecture Considerations, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Madhavi Valluri, Lizy John, and Heather Hanson (University of Texas at Austin), Exploiting Compiler-Generated Schedules for Energy Savings in High-Performance Processors, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

J. S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, and M. Kandemir (Pennsylvania State University), Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Nam Sung Kim and Trevor Mudge (University of Michigan), The Microarchitecture of a Low Power Register File, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, and Kanad Ghose (State University of New York, Binghamton), Power Efficient Comparators for Long Arguments in Superscalar Processors, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Hajime Shimada, Hideki Ando, and Toshio Shimada (Nagoya University), Pipeline Stage Unification: A Low-Energy Consumption Technique for Future Mobile Processors, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Andreas Moshovos (University of Toronto), Checkpointing Alternatives for High Performance, Power-Aware Processors, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Hsien-Hsin S. Lee and Chinnakrishnan S. Ballapuram (Georgia Institute of Technology), Energy Efficient DTLB and Data Cache using Semantic-Aware Multilateral Partitioning, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger (University of Texas at Austin), Microprocessor Pipeline Energy Analysis, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Emil Talpes and Diana Marculescu (Carnegie Mellon University), A Critical Analysis of Application-Adaptive Multiple Clock Processors, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Carlos Molina, Carles Aliagas, Montse Garcia (Universitat Rovira i Virgili), Antonio Gonzalez, and Jordi Tubella (Universitat Politecnica de Catalunya), Non Redundant Data Cache, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Jun Yang, Jia Yu (University of California, Riverside), and Youtao Zhang (University of Texas at Dallas), Lightweight Set Buffer: Low Power Data Cache for Multimedia Application, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Youtao Zhang (University of Texas at Dallas) and Jun Yang (University of California at Riverside), Low Cost Instruction Cache Designs for Tag Comparison Elimination, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Gokhan Memik, Glenn Reinman, and William H. Mangione-Smith (University of California, Los Angeles), Reducing Energy and Delay Using Efficient Victim Caches, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Soontae Kim, N. Vijaykrishnan, M. J. Irwin (The Pennsylvania State University), and L. K. John (The University of Texas at Austin), On Load Latency in Low-Power Caches, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Dan Nicolaescu, Alex Veidenbaum, and Alex Nicolau (University of California, Irvine), Reducing Data Cache Energy Consumption via Cached Load/Store Queue, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, and Kanad Ghose (State University of New York, Binghamton), Reducing Reorder Buffer Complexity Through Selective Operand Caching, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Yiran Chen, Kaushik Roy, and Cheng-Kok Koh (Purdue University), Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Michael D. Powell and T. N. Vijaykumar (Purdue University), Pipeline Muffling and A Priori Current Ramping: Architectural Techniques to Reduce High-Frequency Inductive Noise, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Seongmoo Heo, Kenneth Barr, and Krste Asanovic (Massachusetts Institute of Technology), Reducing Power Density through Activity Migration, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Amit Agarwal and Kaushik Roy (Purdue University), A Noise Tolerant Cache Design to Reduce Gate and Sub-threshold Leakage in the Nanometer Regime, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Yen-Jen Chang, Chia-Lin Yang, and Feipei Lai (National Taiwan University), A Power-Aware SWDR Cell for Reducing Cache Write Power, in the 2003 International Symposium on Low Power Electronics and Design (ISLPED-2003), August 2003.

Lucian N. Vintan, Marius Sbera, Ioan Z. Mihu, and Adrian Florea (University of Sibiu, Romania), An alternative to branch prediction: pre-computed branches, in ACM SIGARCH Computer Architecture News, Volume 31, Issue 3, June 2003.

Erez Perelman, Greg Hamerly, Michael Van Biesbrouck, Timothy Sherwood, and Brad Calder (University of California, San Diego), Using SimPoint for accurate and efficient simulation, in the 2003 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS-2003), poster session, June 2003.

Steven S. Lumetta and Sanjay J. Patel (University of Illinois at Urbana-Champaign), Characterization of essential dynamic instructions, in the 2003 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS-2003), poster session, June 2003.

Sylvain Girbal, Gilles Mouchard (Laboratoire de Recherche en Informatique), Albert Cohen (INRIA Rocquencourt), and Olivier Temam (Laboratoire de Recherche en Informatique), DiST: a simple, reliable and scalable method to significantly reduce processor architecture simulation time, in the 2003 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS-2003), June 2003.

Fen Xie, Margaret Martonosi, and Sharad Malik (Princeton University), Compile-time dynamic voltage scaling settings: opportunities and limits, in the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation (PLDI-2003), June 2003.

Bjorn De Sutter, Hans Vandierendonck, Bruno De Bus, and Koen De Bosschere (Ghent University), On the side-effects of code abstraction, in the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES-2003), June 2003.

Arvind Krishnaswamy and Rajiv Gupta (University of Arizona), Enhancing the Performance of 16bit Code Using Augmenting Instructions, in the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES-2003), June 2003.

Marc L. Corliss, E. Christopher Lewis, and Amir Roth (University of Pennsylvania), A DISE Implementation of Dynamic Code Decompression, in the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES-2003), June 2003.

Nevine AbouGhazaleh, Bruce Childers, Daniel Mosse, Rami Melhem, Matthew Craven (University of Pittsburgh), Energy Management for RealTime Embedded Applications with Compiler Support, in the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES-2003), June 2003.

Zhenlin Wang (University of Massachusetts, Amherst), Doug Burger (University of Texas, Austin), Steven K. Reinhardt (University of Michigan), Kathryn S. McKinley (University of Texas, Austin), Charles C. Weems (University of Massachusetts, Amherst), Guided Region Prefetching: A Cooperative Hardware/Software Approach, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Marc L. Corliss, E. Christopher Lewis, and Amir Roth (University of Pennsylvania), DISE: A Programmable Macro Engine for Customizing Applications, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, and Frank Mueller (North Carolina State University), Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Timothy Sherwood, Suleyman Sair, and Brad Calder (University of California, San Diego), Phase Tracking and Prediction, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Huiyang Zhou, Jill Flanagan, and Thomas M. Conte (North Carolina State University), Detecting Global Stride Locality in Value Streams, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Renju Thomas, Manoj Franklin (University of Maryland, College Park), Chris Wilkerson, and Jared Stark (Intel Corporation), Improving Branch Prediction by Dynamic Dataflow-based Identification of Correlated Branches from a Large Global History, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Rajeev Balasubramonian, Sandhya Dwarkadas, and David H. Albonesi (University of Rochester), Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Ravi Bhargava and Lizy K. John (University of Texas at Austin), Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Dan Ernst, Andrew Hamel, and Todd Austin (University of Michigan), Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Paramjit Oberoi and Gurindar Sohi (University of Wisconsin – Madison), Parallelism in the Front-End, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Michael Huang (University of Rochester), Jose Renau, and Josep Torrellas (University of Illinois at Urbana-Champaign), Positional Adaptation of Processors: Application to Energy Reduction, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Chuanjun Zhang, Frank Vahid, and Walid Najjar (University of California, Riverside), A Highly-Configurable Cache Architecture for Embedded Systems, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar and Irith Pomeranz (Purdue University), Transient-Fault Recovery for Chip Multiprocessors, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, and James C. Hoe (Carnegie Mellon University), SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Michael D Powell and T. N. Vijaykumar (Purdue University), Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Jessica H. Tseng and Krste Asanovic (Massachusetts Institute of Technology), Banked Multiported Register Files for High-Frequency Superscalar Microprocessors, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Ilhyun Kim and Mikko H. Lipasti (UW-Madison), Half-price Architecture, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, and Steven G. Dropsho (University of Rochester), Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan (University of Virginia), and David Tarjan (Swiss Federal Institute of Technology Zurich), Temperature-Aware Microarchitecture, in the 30th Annual International Symposium on Computer Architecture (ISCA-2003), June 2003.

Huiyang Zhou, Thomas M. Conte (North Carolina State University), Enhancing Memory Level Parallelism via Recovery-Free Value Prediction, in the 17th Annual International Conference on Supercomputing (ICS-2003), June 2003.

Nam Sung Kim, Trevor Mudge (University of Michigan), Reducing Register Ports Using Delayed Write-Back Queues And Operand Pre-Fetch, in the 17th Annual International Conference on Supercomputing (ICS-2003), June 2003.

G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, and Srinivas Devadas (Massachusetts Institute of Technology), The AEGIS Processor Architecture for Tamper-Evident and Tamper-Resistant Processing, in the 17th Annual International Conference on Supercomputing (ICS-2003), June 2003.

W. Zhang (Penn State University), M. Karakoy (Imperial College), M. Kandemir, G. Chen (Penn State University), A Compiler Approach for Reducing Data Cache Energy, in the 17th Annual International Conference on Supercomputing (ICS-2003), June 2003.

Jung-Yup Kang (University of Southern California), Saurab Shah (University of California at Irvine), Sandeep Gupta (University of Southern California), and Jean-Luc Gaudiot (University of California at Irvine), An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation, in the IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP-2003), June 2003.

Rama Sangireddy and Arun K. Somani (Iowa State University), Application-Specific Computing with Adaptive Register File Architectures, in the IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP-2003), June 2003.

Jose L. Ayala, Marisa Lopez-Vallejo (Universidad Politecnica de Madrid), Alexander Veidenbaum (University of California, Irvine), and Carlos A. Lopez (Universidad Politecnica de Madrid), Energy Aware Register File Implementation through Instruction Predecode, in the IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP-2003), June 2003.

J. Eliot B. Moss, Charles C. Weems, and Timothy Richards (University of Massachusetts Amherst), The CoGenT Project: Co-Generating Compilers and Simulators For Dynamically Compiled Languages, in the 2003 Workshop on Next Generation Software, held in conjunction with the 2003 International Parallel and Distributed Processing Symposium, April 2003.

Bruce Childers (University of Pittsburgh), Jack Davidson (University of Virginia), and Mary Lou Soffa (University of Pittsburgh), Continuous Compilation: A New Approach to Aggressive and Adaptive Code Transformation, in the 2003 Workshop on Next Generation Software, held in conjunction with the 2003 International Parallel and Distributed Processing Symposium, April 2003.

Chulho Shin (Samsung Electronics Corporation), Seong-Won Lee (University of Southern California), and Jean-Luc Gaudiot (University of California, Irvine), Dynamic Scheduling Issues in SMT Architectures, in the 2003 International Parallel and Distributed Processing Symposium, April 2003.

Ying Chen, Resit Sendag, and David J. Lilja (University of Minnesota), Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor, in the 2003 International Parallel and Distributed Processing Symposium, April 2003.

Sudhanva Gurumurthi, Ning An, Anand Sivasubramaniam, N. Vijaykrishnan, Mahmut Kandemir, and Mary Jane Irwin (The Pennsylvania State University), Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries, in the 2003 International Parallel and Distributed Processing Symposium, April 2003.

Won W. Ro (University of Southern California), Jean-Luc Gaudiot (University of California, Irvine), Stephen P. Crago, and Alvin M. Despain (University of Southern California), HiDISC: A Decoupled Architecture for Data-Intensive Applications, in the 2003 International Parallel and Distributed Processing Symposium, April 2003.

Ho-Seop Kim and James Smith, Dynamic binary translation for accumulator-oriented architectures, in the 2003 International Symposium on Code Generation and Optimization, (CGO-2003), March 2003.

Xianglong Huang (UT Austin), Eliot (UMass Amherst), Steve Blackburn (Australian National University), Kathryn S McKinley, Doug Burger (UT Austin), Dynamic SimpleScalar: simulating Java Virtual Machines, in the 2003 Workshop on Managed Run Time Environment Workloads (MRTE-2003), March 2003.

John Haskins, Jr. and Kevin Skadron, Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation, in the 2003 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2003), March 2003.

Jianwei Chen, Michel Dubois (University of Southern California), and Per Stenstrom (Chalmers University of Technology), Integrating complete-system and user-level performance/power simulators: the SimWattch approach, in the 2003 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2003), March 2003.

Gokhan Memik and William H. Mangione-Smith (University of California, Los Angeles), NEPAL: A Framework for Efficiently Structuring Applications for Network Processors, in the 2003 Workshop on Network Processors (NP2), February 2003.

Mark A. Franklin (Washington University in St. Louis), and Tilman Wolf  (University of Massachusetts at Amherst), Power Considerations in Network Processor Design, in the 2003 Workshop on Network Processors (NP2), February 2003.

Eric Chi, A. Michael Salem, R. Iris Bahar (Brown University), and Richard Weiss (Hampshire College), Combining Software and Hardware Monitoring for improved Power and Performance Tuning, in the 7th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-7), February 2003.

Won W. Ro (University of Southern California) and Jean-Luc Gaudiot (University of California, Irvine), Compiler support for Dynamic Speculative Pre-Execution, in the 7th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-7), February 2003.

Gokhan Memik, Glenn Reinman, and William H. Mangione-Smith (University of California, Los Angeles), Just Say No: Benefits of Early Cache Miss Determination, in the 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), February 2003.

Blaise Gassend, Ed Suh, Dwaine Clarke, Marten van Dijk, and Srinivas Devadas (MIT), Caches and Merkle Trees for Efficient Memory Authentication, in the 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), February 2003.

Joshua J. Yi, David J. Lilja, and Douglas M. Hawkins (University of Minnesota), A Statistically Rigorous Approach for Improving Simulation Methodology, in the 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), February 2003.

Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, and T.N. Vijaykumar (Purdue University), Deterministic Clock Gating For Microprocessor Power Reduction, in the 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), February 2003.

Juan L. Aragón (Universidad de Murcia), José González (Intel Labs), and Antonio González (Universitat Politècnica de Catalunya), Power-Aware Control Speculation through Selective Throttling, in the 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), February 2003.

Russ Joseph (Princeton University), David Brooks (Harvard University), and Margaret Martonosi (Princeton University), Control Techniques to Eliminate Voltage Emergencies in High-Performance Processors, in the 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), February 2003.

Lei Chen, Steve Dropsho, and David H. Albonesi (University of Rochester), Dynamic Data Dependence Tracking and its Application to Branch Prediction, in the 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), February 2003.

Beth Simon, Brad Calder, and Jeanne Ferrante (University of California, San Diego), Incorporating Predicate Information Into Branch Predictors, in the 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), February 2003.

Daniel A. Jimenez (Rutgers University), Reconsidering Complex Branch Predictors, in the 9th Annual International Symposium on High Performance Computer Architecture (HPCA-9), February 2003.

2002

Amir Roth (University of Pennsylvania) and Gurindar Sohi (University of Wisconsin at Madison), A Quantitative Framework for Automated Pre-execution Thread Selection, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Gabriel H. Loh (Yale University), Exploiting Data-Width Locality to Increase Superscalar Execution Bandwidth, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Greg Semeraro, David H. Albonesi, Steven G. Dropsho, Grigorios Magklis, Sandhya Dwarkadas and Michael L. Scott (University of Rochester), Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

K. Basu, A. Choudhary, J. Pisharath (Northwestern University), and M. Kandemir (Pennsylvania State University), Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Steven Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, and Eby G. Friedman (University of Rochester), Managing Static Leakage Energy in Microprocessor Functional Units, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, and David I. August (Princeton University), Microarchitectural Exploration with Liberty, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Nam Sung Kim (University of Michigan), Krisztian Flautner (ARM Ltd), David Blaauw, and Trevor Mudge (University of Michigan), Drowsy Instruction Caches: Leakage Power Reduction using Dynamic Voltage Scaling and Cache Sub-bank Prediction, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

I. Kadayif, A. Sivasubramaniam, M. Kandemir, G. Kandiraju, and G. Chen (Pennsylvania State University), Generating Physical Addresses Directly for Saving Instruction TLB Energy, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Il Park, Michael D. Powell, and T. N. Vijaykumar (Purdue University), Reducing Register Ports for Higher Speed and Lower Energy, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Steven Hsu, Shih-Lien Lu (Intel Corporation), Shih-Chang Lai (Oregon State University), Ram Krishnamurthy, and Konrad Lai (Intel Corporation), Dynamic Addressing Memory Arrays with Physical Locality, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Craig Zilles (University of Illinois at Urbana-Champaign) and Gurindar Sohi (University of Wisconsin at Madison), Master/Slave Speculative Parallelization, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Gregory A. Muthler, David Crowe, Sanjay J. Patel, and Steven S. Lumetta (University of Illinois at Urbana-Champaign), Instruction Fetch Deferral using Static Slack, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Vlad Petric, Anne Bracy, and Amir Roth (University of Pennsylvania), Three Extensions To Register Integration, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

J. Adam Butts and Gurindar S. Sohi (University of Wisconsin-Madison), Characterizing and Predicting Value Degree of Use, in the 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Changkyu Kim, Doug Burger, and Stephen W. Keckler (University of Texas at Austin), An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches, in the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.

J. Adam Butts and Guri Sohi (University of Wisconsin-Madison), Dynamic Dead-Instruction Detection and Elimination, in the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.

Jeffrey Oplinger and Monica S. Lam (Stanford University), Enhancing Software Reliability with Speculative Threads, in the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.

Dongkeun Kim and Donald Yeung (University of Maryland at College Park), Design and Evaluation of Compiler Algorithms for Pre-Execution, in the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.

Ruchira Sasanka, Christopher J. Hughes, and Sarita V. Adve (University of Illinois at Urbana-Champaign), Joint Local and Global Hardware Adaptations for Energy, in the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.

Raksit Ashok, Saurabh Chheda, and Csaba Andras Moritz (University of. Massachusetts, Amherst,), Cool-Mem: Combining Statically Speculative Memory Accessing with Selective Address Translation for Energy Efficiency, in the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.

Timothy Sherwood, Erez Perelman, Greg Hamerly, and Brad Calder (University of California, San Diego), Automatically Characterizing Large Scale Program Behavior, in the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.

Ravi Rajwar and James R. Goodman (University of Wisconsin-Madison), Transactional Lock-Free Execution of Lock-Based Programs, in the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.

Jun Xu, Zbigniew Kalbarczyk, Sanjay Patel and Ravishankar K. Iyer (University of Illinois at Urbana-Champaign), Architecture Support for Defending Against Buffer Overflow Attacks, in the 2002 Workshop on Evaluating and Architecting System dependabilitY (EASY-2002), October 2002.

Hongbo Yang, Guang R. Gao, and Clement Leung (University of Delaware), On Achieving Balanced Power Consumption in Software Pipelined Loops, in the 2002 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2002), October 2002.

Gokhan Memik and William H. Mangione-Smith (University of California, Los Angeles), Increasing Power Efficiency of Multi-Core Network Processors through Data Filtering, in the 2002 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2002), October 2002.

Jayaprakash Pisharath and Alok Choudhary (Northwestern University), An Integrated Approach to Reducing Power Dissipation in Memory Hierarchies, in the 2002 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2002), October 2002.

Bengu Li and Rajiv Gupta (University of Arizona), Bit Section Instruction Set Extension of ARM for Embedded Applications, in the 2002 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2002), October 2002.

Amol Bakshi, Jingzhao Ou, and Viktor K. Prasanna (University of Southern California), Towards Automatic Synthesis of a Class of Application-Specific Sensor Networks, in the 2002 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2002), October 2002.

Mladen Nikitovic and Mats Brorsson (Royal Institute of Technology, KTH), An Adaptive Chip-Multiprocessor Architecture for Future Mobile Terminals, in the 2002 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2002), October 2002.

Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, and Eric Rotenberg (North Carolina State University), A Case for Dynamic Pipeline Scaling, in the 2002 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2002), October 2002.

L. Gomez, L. Pinuel, M. Prieto, and F. Tirado (Universidad Complutense, Madrid), Analysis of Simulation-adapted SPEC 2000 Benchmarks, in ACM SIGARCH Computer Architecture News, Volume 31, Issue 3, September 2002.

Joan-Manuel Parcerisa (Universitat Politècnica de Catalunya), Julio Sahuquillo (Universitat Politècnica de València), Antonio González (Universitat Politècnica de Catalunya), and José Duato (Universitat Politècnica de València), Efficient Interconnects for Clustered Microarchitectures, in the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002), September 2002.

Manel Fern´andez and Roger Espasa (Universitat Polit`ecnica de Catalunya), Speculative Alias Analysis for Executable Code, in the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002), September 2002.

Zhenlin Wang (University of Massachusetts, Amherst), Kathryn S. McKinley (University of Texas, Austin), Arnold L. Rosenberg, and Charles C. Weems (University of Massachusetts, Amherst), Using the Compiler to Improve Cache Replacement Decisions, in the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002), September 2002.

Gabriel H. Loh and Dana S. Henry (Yale University), Predicting Conditional Branches With Fusion-Based Hybrid Predictors, in the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002), September 2002.

Steve Dropshoy, Alper Buyuktosunogluz, Rajeev Balasubramoniany, David H. Albonesiz, Sandhya Dwarkadasy, Greg Semeraroz, Grigorios Magklisy, and Michael L. Scott (University of Rochester), Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power, in the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002), September 2002.

L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and A. Sivasubramaniam (Pennsylvania State University), Leakage Energy Management in Cache Hierarchies, in the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002), September 2002.

Lieven Eeckhout, Hans Vandierendonck, and Koen De Bosschere (Ghent University), Workload Design: Selecting Representative Program-Input Pairs, in the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002), September 2002.

Gautham K. Dorai and Donald Yeung (University of Maryland at College Park), Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance, in the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002), September 2002.

Neungsoo Park, Bo Hong, and Viktor K. Prasanna (University of Southern California), Analysis of Memory Hierarchy Performance of Block Data Layout, in the 2002 International Conference on Parallel Processing (ICPP-2002), August 2002.

Paramjit Oberoi and Gurindar Sohi (University of Wisconsin - Madison), Out-of-Order Instruction Fetch using Multiple Sequencers, in the 2002 International Conference on Parallel Processing (ICPP-2002), August 2002.

Teresa Monreal, Víctor Viñals (Universidad de Zaragoza), Antonio González and Mateo Valero (Universitat Politècnica de Catalunya), Hardware Schemes for Early Register Release, in the 2002 International Conference on Parallel Processing (ICPP-2002), August 2002.

Amirali Baniasadi (Northwestern University) and Andreas Moshovos (University of Toronto), Asymmetric-Frequency Clustering: A Power-Aware Back-End for High-Performance Processors, in the 2002 International Symposium on Low Power Electronics and Design (ISLPED-2002), August 2002.

Chris H. Kim and Kaushik Roy (Purdue University), Dynamic Vt SRAM : A Leakage Tolerant Cache Memory for Low Voltage Microprocessors, in the 2002 International Symposium on Low Power Electronics and Design (ISLPED-2002), August 2002.

Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada (Nagoya University), A Preactivating Mechanism for a VT-CMOS Cache using Address Prediction, in the 2002 International Symposium on Low Power Electronics and Design (ISLPED-2002), August 2002.

Koji Inoue, V.G. Moshnyaga (Fukuoka University), and K. Murakami (Kyushu University), A History-Based I-Cache for Low-Energy Multimedia Applications, in the 2002 International Symposium on Low Power Electronics and Design (ISLPED-2002), August 2002.

Takanori Okuma, Yun Cao, Masanori Muroyama, and Hiroto Yasuura (Kyushu University), Reducing Access Energy of On-Chip Data Memory Considering Active Data Bitwidth, in the 2002 International Symposium on Low Power Electronics and Design (ISLPED-2002), August 2002.

Michael Zhang and Krste Asanovic (MIT), Fine-Grain CAM Tag Cache Resizing Using Miss Tags, in the 2002 International Symposium on Low Power Electronics and Design (ISLPED-2002), August 2002.

D. Cheresiz (Leiden University), B. Juurlink, S. Vassiliadis (Delft University of Technology), and H. Wijshoff (Leiden University), Performance Scalability of Multimedia Instruction Set Extensions, in the 8th International Euro-Par Conference (Euro-Par 2002), August 2002.

J.C. Moure, D.I. Rexachs, and E. Luque (Universidad Autónoma de Barcelona), Speeding Up Target Address Generation Using a Self-indexed FTB, in the 8th International Euro-Par Conference (Euro-Par 2002), August 2002.

J.J. Yi, R. Sendag, and D.J. Lilja (University of Minnesota), Increasing Instruction-Level Parallelism with Instruction Precomputation, in the 8th International Euro-Par Conference (Euro-Par 2002), August 2002.

R. Sendag, D.J. Lilja, and S.R. Kunkel (University of Minnesota), Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions, in the 8th International Euro-Par Conference (Euro-Par 2002), August 2002.

V. Desmet, B. Goeman, and K. De Bosschere (Ghent University), Independent Hashing as Confidence Mechanism for Value Predictors in Microprocessors, in the 8th International Euro-Par Conference (Euro-Par 2002), August 2002.

Lori Carter, and Brad Calder (University of California, San Diego), Using predicate path information in hardware to determine true dependences, in ACM 16th International Conference on Supercomputing (ICS-2002), June 2002.

Juan L. Aragón, José González (Universidad de Murcia), Antonio González (Universitat Politècnica de Catalunya), and James Smith (University of Wisconsin-Madison), Dual path instruction processing, in ACM 16th International Conference on Supercomputing (ICS-2002), June 2002.

Yi Zhang, Steve Haga, Rajeev Barua (University of Maryland, College Park), Execution history guided instruction prefetching, in ACM 16th International Conference on Supercomputing (ICS-2002), June 2002.

Jih-Kwon Peir (University of Florida), Shih-Chang Lai (Oregon State University), Shih-Lien Lu, Jared Stark, and Konrad Lai (Intel Labs), Bloom filtering cache misses for accurate data speculation and prefetching, in ACM 16th International Conference on Supercomputing (ICS-2002), June 2002.

Gurhan Kucuk Dmitry Ponomarev, and Kanad Ghose (State University of New York, Binghamton), Low-complexity Reorder Buffer Architecture, in ACM 16th International Conference on Supercomputing (ICS-2002), June 2002.

Shih-Chang Lai (Oregon State University), Shih-Lien Lu, Konrad Lai (Intel Corporation), Jih-Kwon Peir (University of Florida), Ditto Processor, in the International Performance and Dependability Symposium, June 2002.

Ricardo Lopes (Universidade do Porto), Luis F. Castro (State U. of New York, Stony Brook, USA), and Vitor Santos Costa (U. of Wisconsin at Madison, USA), From Simulation to Practice: Cache Performance Study of a Prolog System, in ACM SIGPLAN Workshop on Memory System Performance (MSP 2002), June 2002.

Gokul B. Kandiraju and Anand Sivasubramaniam (Pennsylvania State University), Characterizing the d-TLB Behavior of SPEC CPU2000 Benchmarks, in ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS '02), June 2002.

Gabriel H. Loh and Dana S. Henry (Yale University), Applying Machine Learning for Ensemble Branch Predictors, in the Proceedings of the 2002 Industrial and Engineering Applications of Artificial Intelligence and Expert Systems (IEAAIE 2002), June 2002.

Dan Ernst and Todd Austin, Efficient Dynamic Scheduling Through Tag Elimination, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Alvin R. Lebeck, Jinson Koppanalil, Tong Li, Jaidev Patwardhan, and Eric Rotenberg, A Large, Fast Instruction Window for Tolerating Cache Misses, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Ashutosh S. Dhodapkar and James E. Smith, Managing Configurable Hardware via Dynamic Working Set Analysis, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Rastislav Bodik and Mark Hill, Slack: Maximizing Performance Under Technological Constraints, Brian Fields, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, and Trevor Mudge, Drowsy Caches: Techniques for Reducing Leakage Power, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Seongmoo Heo, Ken Barr, Mark Hampton, and Krste Asanovic, Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bitlines, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

M.S. Hrishikesh, Norman P. Jouppi, Keith I. Farkas, Doug Burger, Stephen W. Keckler, and Premkishore Shivakumar, The Optimal Useful Logic Depth Per Pipeline Stage is 6-8 FO4, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Zhigang Hu Stefanos Kaxiras, and Margaret Martonosi, Timekeeping in the Memory System: An Efficient Approach to Predicting and Optimizing Memory Behavior, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Ilhyun Kim and Mikko Lipasti, Implementing Optimizations at Decode Time, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Diana Marculescu, Sim-GALS: A Globally Asynchronous-Locally Synchronous Processor Simulation Environment, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Gokul B. Kandiraju and Anand Sivasubramaniam, Going the Distance for TLB Prefetching: An Application-driven Study, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Ho-Seop Kim and James E. Smith, An Instruction Set Architecture and Microarchitecture for Instruction Level Distributed Processing, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Alex Pajuelo, Antonio Gonzalez, and Mateo Valero, Speculative Dynamic Vectorization, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Steven E. Raasch, Nathan L. Binkert, and Steven K. Reinhardt, A Scalable Instruction Queue Using Dependence Chains, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

T. N. Vijaykumar, Irith Pomeranz, and Karl K. Cheng, Transient Fault Recovery Using Simultaneous Multithreading, in the 29th Annual International Symposium on Computer Architecture (ISCA 2002), May 2002.

Weiyu Tang, Alexander Veidenbaum, Alexandru Nicolau and Rajesh Gupta (UC-Irvine), Integrated I-cache Way Predictor and Branch Target Predictor to Reduce Power Consumption, in the Fourth International Symposium on High Performance Computing (ISHPC-IV), May 2002.

Glenn Reinman (UCLA), Brad Calder (UC - San Diego) and Todd Austin (University of Michigan), High Performance and Energy Efficient Serial Prefetch Architecture, in the Fourth International Symposium on High Performance Computing (ISHPC-IV), May 2002.

Chia-Lin Yang and Alvin Lebeck (Duke University), A Programmable Memory Hierarchy for Prefetching Linked Data, in the Fourth International Symposium on High Performance Computing (ISHPC-IV), May 2002.

Dana S. Henry, Gabriel H. Loh and Rahul Sami (Yale University), Speculative Clustered Caches for Clustered Processors, in the Fourth International Symposium on High Performance Computing (ISHPC-IV), May 2002.

Lori Carter, Weihaw Chuang and Brad Calder (UC - San Diego), An EPIC Processor with Pending Functional Units, in the Fourth International Symposium on High Performance Computing (ISHPC-IV), May 2002.

Joon-Sang Park, Michael Penner, and Viktor K. Prasanna (University of Southern California), Optimizing Graph Algorithms for Improved Cache Performance, In Proceedings of the International Parallel and Distributed Processing Symposium, April 2002.

Gokhan Memik, Seda O. Memik, Bill Mangione-Smith (University of California, Los Angeles), Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic, in the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’02), April 2002.

Mihai Budiu, Mahim Mishra, Ashwin Bharambe, and Seth C. Goldstein (CMU), Peer-to-peer Hardware-software Interfaces for Reconfigurable Fabrics, in the 2002 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '02), April 2002.

Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose (State University of New York, Binghamton), AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors, in the 5th Design, Automation and Test in Europe Conference (DATE-02), Paris, France, March 2002.

Azevedo, I Issenin, R Cornea, R Gupta, N Dutt, A Veidenbaum and A Nicolau (University of California, Irvine), Profile-Based Dynamic Voltage Scaling using Program Checkpoints, in the 5th Design, Automation and Test in Europe Conference (DATE-02), Paris, France, March 2002.

I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and A. Sivasubramaniam (Pennsylvania State University), EAC: A Compiler Framework for High-Level Energy Estimation and Optimization, in the 5th Design, Automation and Test in Europe Conference (DATE-02), Paris, France, March 2002.

Weiyu Tang Rajesh Gupta Alexandru Nicolau (University of California, Irvine), Power Savings in Embedded Processors through Decode Filter Cache, in the 5th Design, Automation and Test in Europe Conference (DATE-02), Paris, France, March 2002.

Peter Petrov and Alex Orailoglu (University of California, San Diego), Power Efficient Embedded Processor IP’s through Application Specific Tag Compression in Data Caches, in the 5th Design, Automation and Test in Europe Conference (DATE-02), Paris, France, March 2002.

Haiyong Xie, Laxmi Bhuyan and Yeim-Kuan Chang (UC - Riverside), Benchmarking Web Server Architectures: A Simulation Study on Micro Performance, in the Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-02), February 2002.

Harold W. Cain, Kevin M. Lepak, Brandon A. Schwartz and Mikko H. Lipasti (University of Wisconsin - Madison), Precise and Accurate Processor Simulation, in the Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-02), February 2002.

C.-H. Hsu and U. Kremer (Rutgers University), Single Region vs. Multiple Regions: A Comparison of Different Compiler-Directed Dynamic Voltage Scheduling Approaches, in Power-Aware Computer Systems, B. Falsafi and T.N. Vijaykumar eds., February 2002.

Suleyman Sair, Timothy Sherwood, and Brad Calder, Quantifying Load Stream Behavior, in the 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002.

Martin Kampe, Per Stenstrom, and Michel Dubois, The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches, in the 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002.

Dharmesh Parikh, Kevin Skadron, Yan Zhang, Marco Barcella, and Mircea Stan, Power Issues Related to Branch Prediction, in the 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002.

Yiannakis Sazeides, Modeling Value Speculation, in the 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002.

G. Semeraro, G. Magklis, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, and M. L. Scott, Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling, in the 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002.

Kevin Skadron, Mircea Stan, and Tarek Abdelzaher, Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management, in the 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002.

Osman S. Unsal, Israel Koren, C. Mani Krishna, and Csaba Andras Moritz, The Minimax Cache: An Energy-Efficient Framework for Media Processors, in the 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002.

Se-Hyun Yang, M. D. Powell, Babak Falsafi and T. N. Vijaykumar, Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay, in the 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002.

Zhichun Zhu, Zhao Zhang, and Xiaodong Zhang, Fine-grain Priority Scheduling for Memory-Intensive Applications, in the 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002.

Haiyong Xie, Li Zhou, and Laxmi Bhuyan (University of California, Riverside), Architectural Analysis of Cryptographic Applications for Network Processors, in the 2002 Workshop on Network Processors, held in conjunction with the 8th International Symposium on High Performance Computer Architecture (HPCA-8), February 2002.

Patrick Crowley and Jean-Loup Baer (University of Washington), A Modeling Framework for Network Processor Systems, in the 2002 Workshop on Network Processors, held in conjunction with the 8th International Symposium on High Performance Computer Architecture (HPCA-8), February 2002.

Frederick M. Smith (Cornell University), Certified Run-time Code Generation, Ph.D. Thesis, Cornell University, January 2002.

2001

Michael Huang, Jose Renau, and Josep Torrellas (University of Illinois), Profile-Based Energy Reduction for High Performance, in the 4th Workshop on Feedback-Directed and Dynamic Optimization (FDDO-4), December 2001.

Daniel Jimenez and Calvin Lin (University of Texas at Austin), Branch Path Re-Aliasing, in the 2001 International Conference on High Performance Computing (HiPC-2001), December 2001.

Juan L. Aragón, José González, José M. García (Universidad de Murcia), and Antonio González (Universitat Politecnica de Catalunya), Confidence Estimation for Branch Prediction Reversal, in the 2001 International Conference on High Performance Computing (HiPC-2001), December 2001.

Deepak Babu M.I, Lakshmi Narayanan B, Madhu Saravana Sibi G., and Ranjani Parthasarthi (Anna University, India), Functional Unit Usage Based Thread Selection in a Simultaneous Multithreaded Processor, in the 2001 International Conference on High Performance Computing (HiPC-2001), December 2001.

Srinath Gunasekaran, Sundaram Subramanian, Venkatesan Packirisamy, and Ranjani Parthasarthy (Anna University, India), Hardware Assisted Profile Information Collection and Reuse, in the 2001 International Conference on High Performance Computing (HiPC-2001), December 2001.

Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi, Reducing the Complexity of the Register File in Dynamic Superscalar Processors, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Chen-Yong Cher and T. N. Vijaykumar, Skipper: A Microarchitecture for Exploiting Control-Flow Independence, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Brian Fahs, Satarupa Bose, Matthew Crum, Gregory Muthler, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, and Steven S. Lumetta, Performing Dynamic Optimizations using the rePLay Microarchitecture, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Masashiro Goshima, Kengo Nishino, Yasuhiko Nakashima, Shin-ichiro Mori, Toshiaki Kitamura, and Shinji Tomita, A high-speed dynamic instruction scheduling scheme for superscalars, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Karthikeyan Sankaralingam, Ramadass Nagarajan, Doug Burger, and Stephen W. Keckler, A Design Space Evaluation of Grid Processor Architectures, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Byung-Kwon Chung, Lu Peng, Jih-Kwon Peir, and Konrad Lai, Direct Load: Dependence-Linked Dataflow Resolution of Load Address and Cache Coordinates, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Dmitry V. Ponomarev, Gurhan Kucuk, and Kanad Ghose, Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Michael D. Powell, Amit Agrawal, T.N. Vijaykumar, Babak Falsafi, and Kaushik Roy, Reducing Set-Associative Cache Energy via Selective Direct-Mapping and Way Prediction, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Ravi Rajwar and James R. Goodman, Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Joydeep Ray, James C. Hoe, and Babak Falsafi, Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Eric Rotenberg, Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Osman S. Unsal, Raksit Ashok, Israel Koren, C. M. Krishna, Csaba Andras Moritz, Cool-Cache for Hot Multimedia, in the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

K. Skadron, M. Humphrey, B. Huang, E. Hilton, J. Luo, and P. Allaire (University of Virginia), The Use of Mini-Vector Instructions for Implementing High-Speed Feedback Controllers on General-Purpose Computers, in Proceedings of the 3rd Workshop on Media and Stream Processors, in conjunction with the 34th International Symposium on Microarchitecture (MICRO-34), December 2001.

Tor Aamodt, Andreas Moshovos, and Paul Chow (University of Toronto), The Predictability of Computations that Produce Unpredictable Outcomes, in the Proceedings of the 5th Workshop on Multithreaded Execution, Architecture, and Compilation (MTEAC-5), December, 2001.

Abderazek Ben. A., Mudar S., and Sowa M. (The University of Electro-Communications, Japan), Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors, in IEICE Transaction on Fundamental of Electronics, Communications and Computer Science, Vol.E83-A No.12, December 2001.

Gokhan Memik, William H. Mangione-Smith, Wendong Hu (University of California, Los Angeles), NetBench: A Benchmarking Suite for Network Processors, in the IEEE/ACM International Conference on Computer Aided Design (ICCAD-2001), November, 2001.

Prabhat Jain, Srinivas Devadas, Daniel Engels, Larry Rudolph (Massachusetts Institute of Technology), Software-Assisted Cache Replacement Mechanisms for Embedded Systems, in the IEEE/ACM International Conference on Computer Aided Design (ICCAD-2001), November, 2001.

Diana Marculescu, Anoop Iyer (CMU), Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis, in the IEEE/ACM International Conference on Computer Aided Design (ICCAD-2001), November, 2001.

Chung-Hsing Hsu, Ulrich Kremer, and Michael Hsiao (Rutgers University), Compiler-Directed Dynamic Frequency and Voltage Scheduling, in Power-Aware Computer Systems, B. Falsafi and T.N. Vijaykumar eds., November 2001.

Roberto Maro, Yu Bai, and R. Iris Bahar (Brown University), Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors, in Power-Aware Computer Systems, B. Falsafi and T.N. Vijaykumar eds., November 2001.

Soraya Ghiasi and Dirk Grunwald (Unversity of Colorado - Boulder), A Comparison of Two Architectural Power Models, in Power-Aware Computer Systems, B. Falsafi and T.N. Vijaykumar eds., November 2001.

G. Kuzmanov, S. Vassiliadis and J. van Eindhoven (Delft University of Technology), An Implementation of the MPEG-4 ACQ Function, in the 2001 Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), November 2001.

A. Laffely, J. Liang, P. Jain, N. Weng, W. Burleson and R. Tessier (University of Massachusetts at Amherst), Adaptive Systems on a Chip (aSoC) for Low-Power Signal Processing, in the Proceedings of the Asilomar Conference on Signals, Systems, and Computers, November 2001.

Wen-Tsong Shiue and Chaitali Chakrabarti (Oregon State University), Memory Design and Exploration for Low Power, Embedded Systems, in the Journal of VLSI Signal Processing - Systems for Signal, Image, and Video Technology, Vol. 29, No. 3, November 2001.

M. Miranda, C. Ghez, F. Catthoor, C. Kulkarni, and D. Verkest (IMEC Labs), Systematic Speed-Power Memory Data-Layout Exploration for Cache Controlled Embedded Multimedia Applications, in the 14th International Symposium on System Synthesis (ISSS 2001), October 2001.

P. Petrov and A. Orailoglu (University of California, San Diego), Data Cache Energy Minimization Through Programmable Tag Size Matching to the Applications, in the 14th International Symposium on System Synthesis (ISSS 2001), October 2001.

K.-W. Choi and A. Chatterjee (Georgia Institude of Technology), Efficient Instruction-Level Optimization for Low-Power Embedded Systems, in the 14th International Symposium on System Synthesis (ISSS 2001), October 2001.

K. Sundaramoorthy, Z. Purser, and E. Rotenberg (North Carolina State University), Multipath Execution on Chip Multiprocessors Enabled by Redundant Threads, NCSU ECE Technical Report CESR-TR-01-2, October 2001.

G.Kuzmanov, S.Vassiliadis, and J. van Eijndhoven (Delft University of Technology), MPEG-4 Addressing and ACQ Function, in the Proceedings of the Second Workshop on Embedded Systems and Software (PROGRESS 2001), October 2001.

Michael Penner and Viktor Prasanna (University of Southern California), Cache-Friendly Implementations of Transitive Closure, in the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Hongbo Yang, Guang R. Gao, Andres Marquez, George Cai, and Ziang Hu (University of Delaware), Power and Energy Impact of Loop Transformations,  in the Workshop on Compilers and Operating Systems for Low Power, held in conjunction with the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Enric Morancho, Jose Maria Llaberia and Angel Olive (Universitat Politecnica de Catalunya, Spain), Recovery mechanism for latency misprediction, in the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Nicholas Kohout, Seungryul Choi, Dongkeun Kim, Donald Yeung (University of Maryland at College Park), Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes, in the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Daniel Jimenez, Heather Hanson and Calvin Lin (University of Texas at Austin), Boolean Formula-based Branch Prediction for Future Technologies, in the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Ben Juurlink, Dmitri Tcheressiz, Stamatis Vassiliadis, Harry Wijshoff (Delft University of Technology and Leiden University), Implementation and Evaluation of the Complex Streamed Instruction Set, in the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Huiyang Zhou, Mark Toburen, Eric Rotenberg and Thomas Conte (North Carolina State University), Adaptive Mode Control: A Static-Power-Efficient Cache Design, in the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Tim Sherwood, Erez Perelman and Brad Calder (University of California, San Diego), Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications, in the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Sebastien Nussbaum and James Smith (University of Wisconsin-Madison), Modeling Superscalar Processors via Statistical Simulation, in the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Karthik Sankaranarayanan and Kevin Skadron (University of Virginia), A Scheme for Selective Squash and Re-issue for Single-Sided Branch Hammocks, in the Works in Progress Session of the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Maurício L. Pilla, Philippe O. A. Navaux (Federal University of Rio Grande do Sul), Amarildo T. da Costa (Military Institute of Engineering), and Felipe M. G. Franca (Federal University of Rio de Janeiro), Predicting Trace Inputs with Dynamic Trace Memoization: Determining Speedup Upper Bounds, in the Works in Progress Session of the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Matthew Ziegler, Adam Spanberger, Ganesh Pai, Mircea Stan, and Kevin Skadron (University of Virginia), Dynamic Way Allocation for High Performance, Low Power Caches, in the Works in Progress Session of the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Deependra Talla and Lizy K. John (University of Texas, Austin), A Decoupled Architecture for Accelerating Multimedia, in the 2001 Workshop on Memory Access Decoupled Architectures and Related Issues (MEDEA'01), held in conjuction with the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Jerry Hom and Ulrich Kremer (Rutgers University), Energy Management of Virtual Memory on Diskless Devices, in the 2001 Workshop on Compilers and Operating Systems for Low Power, held in conjuction with the International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001.

Duarte, D., Vijaykrishnan, N., Irwin, M.J. and Kandemir M. (Penn State University), Evaluating the Impact of Architectural-level Optimzations on Clock Power, in the Proceedings of the 14th Annual IEEE International ASIC/SOC Conference, September 2001.

Juan L. Aragon, Jose Gonzalez, Jose M. Garcia (Universidad de Murcia, Spain), and Antonio Gonzalez (Universitat Politècnica de Catalunya. Spain), Selective Branch Prediction Reversal by Correlating with Data Values and Control Flow, in the Proceedings of the International Conference on Computer Design (ICCD-2001), September 2001.

Heather Hanson, M.S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, and Doug Burger, Static Energy Reduction Techniques for Microprocessor Caches, in the Proceedings of the International Conference on Computer Design (ICCD-2001), September 2001.

Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin, and Sudhanva Gurumurthi (Pennsylvania State University), Analyzing energy behavior of spatial access methods for memory-resident data, in the 27th International Conference on Very Large Data Bases (VLDB-2001), September 2001.

Stamatis Vassiliadis, George Kuzmanov, and Stephan Wong (Delft University of Technology), MPEG-4 and the New Multimedia Architectural Challanges, in the Proceedings of the 15th International Conference on Systems for Automation of Engineering and Research (SAER-2001), September 2001.

Rolf Enzler, Marco Platzner, Christian Plessl, Lothar Thiele and Gerhard Troester (Swiss Federal Institute of Technology), Reconfigurable Processors for Handhelds and Wearables: Application Analysis, In Reconfigurable Technology FPGAs and Reconfigurable Processors for Computing and Communications III (ITCom 2001), Proceedings of SPIE, August 2001.

Amirali Baniasadi (Northwestern University), Andreas Moshovos (University of Toronto), Instruction Flow-Based Front End Throttling for Power-Aware High Performance Processors, in the International Symposium on Low Power Electronics and Design (ISLPED-01), Huntington Beach, California, August 2001.

Jun Yang and Rajiv Gupta (University of Arizona), Energy Efficient Load and Store Reuse, in the International Symposium on Low Power Electronics and Design (ISLPED-01), Huntington Beach, California, August 2001.

Russ Joseph, Margaret Martonosi (Princeton University), Run-Time Power Estimation in High Performance Microprocessors, in the International Symposium on Low Power Electronics and Design (ISLPED-01), Huntington Beach, California, August 2001.

Chung-Hsing Hsu, Ulrich Kremer, Michael Hsiao (Rutgers University), Compiler Directed Dynamic Voltage/Frequency Scheduling for Energy Reduction in Microprocessors, in the International Symposium on Low Power Electronics and Design (ISLPED-01), Huntington Beach, California, August 2001.

Emil Talpes, Diana Marculescu (CMU), Power Reduction Through Work Reuse, in the International Symposium on Low Power Electronics and Design (ISLPED-01), Huntington Beach, California, August 2001.

Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev (SUNY Binghamton), and Peter Kogge (University of Notre Dame), Energy Efficient Instruction Dispatch Buffer Design for Superscalar Processors, in the International Symposium on Low Power Electronics and Design (ISLPED-01), Huntington Beach, California, August 2001.

Manel Fernández, Roger Espasa, and Saumya Debray (Universitat Polit`ecnica de Catalunya, Spain), Load Redundancy Elimination on Executable Code, in the 2001 European Conference on Parallel Computing (Euro-Par 2001), August 2001.

Alex Ramirez, Josep L. Larriba-Pey, and Mateo Valero (Universitat Polit`ecnica de Catalunya, Spain), Branch Prediction Using Profile Data, in the 2001 European Conference on Parallel Computing (Euro-Par 2001), August 2001.

M. Anton Ertl and David Gregg (Trinity College, Ireland), The Behavior of Efficient Virtual Machine Interpreters on Modern Architectures, in the 2001 European Conference on Parallel Computing (Euro-Par 2001), August 2001.

Dmitri Tcheressiz (Leiden University, The Netherlands), Ben Juurlink, Stamatis Vassiliadis (Delft University of Technology, The Netherlands), and Harry Wijsho (Leiden University, The Netherlands), Performance of the Complex Streamed Instruction Set on Image Processing Kernels, in the 2001 European Conference on Parallel Computing (Euro-Par 2001), August 2001.

K.M. Kavi, R. Giorgi, J. Arul (University of Alabama at Huntsville), Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation, IEEE Transactions on Computers, Vol. 50, No. 8, August 2001.

S. Vassiliadis and S. Wong and S. Cotofana (Delft University of Technology), The MOLEN rm-coded Processor, in the Proceedings of the 11th International Conference on Field-Programmable Logic and Applications 2001 (FPL2001), August 2001.

M. Postiff, D. Greene, S. Raasch, and T. Mudge (University of Michigan), Integrating Superscalar Processor Components to Implement Register Caching, in the 2001 International Conference on Supercomputing (ICS-01), July 2001.

Ramon Canal and Antonio Gonzalez (Universitat Politecnica de Catalunya, Spain), Reducing the complexity of the issue logic, in the 2001 International Conference on Supercomputing (ICS-01), July 2001.

Nathan T. Slingerland and Alan Jay Smith (University of California, Berkeley), Cache performance for multimedia applications, in the 2001 International Conference on Supercomputing (ICS-01), July 2001.

Andreas Moshovos (University of Toronto), Dionisios N. Pnevmatikatos (Technical University of Crete), and Amirali Baniasadi (Northwestern University), Slice-processors: an implementation of operation-based prediction, in the 2001 International Conference on Supercomputing (ICS-01), July 2001.

Abdel-Hameed A. Badawy, Aneesh Aggarwal, Donald Yeung, and Chau-Wen Tseng (University of Maryland), Evaluating the Impact of Memory System Performance on Software Prefetching and Locality Optimizations, in the 2001 International Conference on Supercomputing (ICS-01), July 2001.

Craig Zilles and Gurindar Sohi (University of Wisconsin-Madison), Execution-based Prediction Using Speculative Slices, in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, July 2001.

Rajeev Balasubramonian, Sandhya Dwarkadas, and David Albonesi (University of Rochester), Dynamically Allocating Processor Resources Between Nearby and Distant ILP, in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, July 2001.

Murali M Annavaram, Jignesh M Patel, and Edward S Davidson (University of Michigan), Data Prefetching by Dependence Graph Precomputation, in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, July 2001.

Vinodh Cuppu and BruceJacob (University of Maryland), Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance?, in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, July 2001.

Brian A Fields, Shai Rubin and Rastislav Bodik (University of Wisconsin-Madison), Focusing Processor Policies via Critical-Path Prediction, in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, July 2001.

Lisa Wu, Chris Weaver, and Todd Austin (University of Michigan), CryptoManiac: A Fast Flexible Architecture for Secure Communication, in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, July 2001.

An-Chow Lai, Cem Fide (Purdue University), and Babak Falsafi (Carnegie Mellon University), Dead-Block Prediction & Dead-Block Correlating Prefetchers, in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, July 2001.

Daniele Folegnani and Antonio Gonzalez (Universitat Politecnica de Catalunya, Spain), Energy-Effective Issue Logic, in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, July 2001.

Subramanya Sastry, Rastislav Bodik, and James Smith (University of Wisconsin-Madison), Rapid Profiling via Stratified Sampling, in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, July 2001.

Arun K. Somani and Joel Nickel (Iowa State University), REESE: A Method of Soft Error Detection in Microprocessors, in the International Conference on Dependable Systems and Networks (DSN-2001), Goteborg, Sweden, July 2001.

Chris Weaver and Todd Austin (University of Michigan), A Fault Tolerant Approach to Microprocessor Design, in the International Conference on Dependable Systems and Networks (DSN-2001), Goteborg, Sweden, July 2001.

William Yurcik (Illinois State University), Gregory S. Wolffe (Grand Valley State University), and Mark A. Holliday (Western Carolina University), A Survey of Simulators Used in Computer Organization/Architecture Courses, in the Proceedings of the 2001 Summer Computer Simulation Conference (SCSC 2001), July 2001.

Derek Chiou, Srinivas Devadas, Josh Jacobs, Prabhat Jain, Vinson Lee, Enoch Peserico, Peter Portante, Larry Rudolph, G. Edward Suh, DanWillenson (Massachusetts Institute of Technology), Scheduler-Based Prefetching for Multilevel Memories, Computation Structures Group Memo 444, July 2001.

Sangyeun Cho, Pen-Chung Yew (University of Minnesota), and Gyungho Lee (Iowa State University), A High-Bandwidth Memory Pipeline for Wide Issue Processors, in IEEE Transactions on Computers, Vol. 50, No. 7, July 2001.

K.M. Hazelwood, M.C. Toburen and T.M. Conte (North Carolina State University), A Case for Exploiting Memory-Access Persistence, in the 2001 Workshop on Memory Performance Issues, held in conjunction with the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, June 2001.

O.S. Unsal, Z. Wang, I. Koren, C.M. Krishna and C.A. Moritz (University of Massachusetts), On Memory Behavior of Scalars in Embedded Multimedia Systems, in the 2001 Workshop on Memory Performance Issues, held in conjunction with the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, June 2001.

Z. Hu, M. Martonosi, and S. Kaxiras (Princeton University), Improving Cache Power Efficiency with an Asymmetric Set-Associative Cache, in the 2001 Workshop on Memory Performance Issues, held in conjunction with the 28th Annual International Symposium on Computer Architecture (ISCA-2001), Goteborg, Sweden, June 2001.

Eric Schnarr and Mark Hill (University of Wisconsin-Madison) and James Larus (Microsoft Research), Facile: A Language and Compiler for High-Performance Processor Simulators, in the ACM SIGPLAN 2001 Conference on Programming Language Design and Implementation (PLDI-2001), Snowbird, Utah, June 2001.

Gabriel H. Loh (Yale University), A Time-Stamping Algorithm for Efficient Performance Estimation of Superscalar Processors, in the 2001 ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS '01), June 2001.

P. Petrov and A. Orailoglu (University of California, San Diego), Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors, in Design Automation Conference (DAC-01), June 2001.

Ledeczi A., Maroti M., Bakay A., Karsai G., Garrett J., Thomason IV C., Nordstrom G., Sprinkle J., and Volgyesi P. (Vanderbilt University), The Generic Modeling Environment, in the 2000 Workshop on Intelligent Signal Processing, May 2001.

Dorit Naishlos, Joseph Nuzman, Chau-Wen Tseng, and Uzi Vishkin (University of Maryland, College Park), Evaluating the XMT Parallel Programming Model, in the 6th Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS-6), April 2001.

Zhenlin Wang, Kathryn S. McKinley, and Arnold L. Rosenberg (University of Massachusetts, Amherst), Improving Replacement Decisions in Set-Associative Caches, in the Proceedings of the MidAtlantic Student Workshop on Programming Languages and Systems (MASPLAS’01), April 2001.

Chris Weaver, Kenneth C. Barr, Eric D. Marsman, Dan Ernst, and Todd Austin (University of Michigan), Performance Analysis Using Pipeline Visualization, in the 2001 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2001), June 2001.

Lieven Eeckhout and Koen De Bosschere (Ghent University), Early Design Phase Power/Performance Modeling through Statistical Simulation, in the 2001 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2001), June 2001.

Eric Larson, Saugata Chatterjee, and Todd Austin (University of Michigan), The MASE Microarchitecture Simulation Environment, in the 2001 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2001), June 2001.

G. Edward Suh, Enoch Peserico, Srinivas Devadas and Larry Rudolph (Massachusetts Institute of Technology), Job-Speculative Prefetching: Eliminating Page Faults From Context Switches in Time-Shared Systems, MIT Computation Structures Group Memo 442, June 2001.

R. Enzler and M. Platzner (Swiss Federal Institute of Technology), Application-Driven Design of Dynamically Reconfigurable Processors, Technical Report TR-01, Swiss Federal Institute of Technology (ETH), March 2001.

A. Iyer and D. Marculescu (CMU), Power Aware Microarchitecture Resource Scaling, in the 2000 Design, Automation and Test in Europe Conference (DATE-2000), March 2001.

C.Kulkarni, C.Ghez, M.Miranda, F.Catthoor, and H.De Man, Cache Conscious Data Layout Organization For Embedded Multimedia Applications, in the 2000 Design, Automation and Test in Europe Conference (DATE-2000), March 2001.

Dah-Lih Jeng and Liang-chuan Hsu (Chung-Cheng Institute of Technology), Some Ideas on Improving Compilation Techniques for Reducing Power Consumption, in the Proceedings of the Seventh Workshop on Compiler Techniques for High-Performance Computing (CTHPC 2001), March 2001.

Michael Powell (Purdue University), Se-Hyun Yang (CMU), Babak Falsafi (CMU), Kaushik Roy, and T. N. Vijaykumar (Purdue University), Reducing Leakage in a High-Performance Deep-Submicron Instruction Cache, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 1, February 2001.

H.H.-S. Lee, M. Smelyanskiy, C.J. Newburn, G.S. Tyson (University of Michigan), Stack value file: custom microarchitecture for the stack, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

A. Roth and G. Sohi (University of Wisconsin), Speculative data-driven multithreading, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

S. Yang (CMU), M.D. Powell (Purdue University), B. Falsafi (CMU), K. Roy, and T.N. Vijaykumar (Purdue University), An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

D. Brooks and M. Martonosi (Princeton University), Dynamic thermal management for high-performance microprocessors, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

B. Goeman, H. Vandierendonck, and K. de Bosschere (Ghent University), Differential FCM: increasing value prediction accuracy by improving table usage efficiency, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

C. Zilles and G. Sohi (University of Wisconsin, Madison), A programmable co-processor for profiling, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

M. Annavaram, J. Patel, E. Davidson (University of Michigan), Call graph prefetching for database applications, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

V. Srinivasan, E. Davidson, G. Tyson, M. Charney, and T. Puzak (University of Michigan), Branch history guided instruction prefetching, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

Wei-Fen Lin, S. Reinhardt, and D. Burger, Reducing DRAM latencies with an integrated memory hierarchy design, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

Daniel A. Jimenez and Calvin Lin (University of Texas at Austin), Neural Methods for Dynamic Branch Prediction, in the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), February 2001.

Stephan Wong, Sorin Cotofana, and Stamatis Vassiliadis (Delft University of Technology), Coarse Reconfigurable Multimedia Unit Extension, Proceedings of the 9th Euromicro Workshop on Parallel and Distributed Processing (PDP 2001), February 2001.

M. J. Irwin, M. Kandemir, and N. Vijaykrishnan (Penn State), SimplePower: A Cycle-Accurate Energy Simulator, in IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, January 2001.

Joseph Arul (University of Alabama in Huntsville), Execution Performance of the Scheduled Dataflow Architecture, in IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, January 2001.

Ana Azevedo, Radu Cornea, Ilya Issenin, Rajesh Gupta, Nikil Dutt, Alex Nicolau, Alex Veidenbaum (University of California, Irvine), Architectural and Compiler Strategies for Dynamic Power Management in the COPPER Project, in the 2001 International Workshop on Innovative Architecture (IWIA-2001), January, 2001.

Renato J. Figueiredo, Jose' A. B. Fortes, Rudolf Eigenmann, Nirav H. Kapadia (Purdue University), Valerie Taylor, Alok Choudhary, Luis Vidal (Northwestern University), and Jan-Jo Chen (Chicago State University), On the Use of Simulation and Parallelization Tools in Computer Architecture and Programming Courses, in Computers in Education Journal. Vol. 11, No. 1, January 2001.

Moure J. C., Rexachs D. I., and Luque E. (University Autónoma of Barcelona, Spain), Fetch Unit Design for Scalable Simultaneous Multithreading (ScSMT), in the Journal of Computer Science & Technology, Vol.1 - No.4, January 2001.

2000

A. Parikh, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin (Pennsylvania State University), Energy-Aware Instruction Scheduling, in the 2001 International Conference on High Performance Computing (HiPC-2001), December 2001.

Kanad Ghose, Dmitry Ponomarev, Gurhan Kucuk, Andrew Flinders (State University of New York, Binghamton), Peter Kogge (University of Notre Dame), Nikzad Toomarian  (State University of New York, Binghamton), Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors, in the 2000 Kool Chips Workshop, held in conjuction with the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

Peter M. Kogge, Vincent W. Freeh (University of Notre Dame), Kanad Ghose (State University of New York, Binghamton), Nikzad (Benny) Toomarian, and Nazeeh Aranki (Jet Propulsion Lab), Morph: Adding an Energy Gear to a High Performance Microarchitecture for Embedded Applications, in the 2000 Kool Chips Workshop, held in conjuction with the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

Jason Casmira and Dirk Grunwald (University of Colorado), Dynamic Instruction Scheduling Slack, in the 2000 Kool Chips Workshop, held in conjuction with the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

Bruce R. Childers, Hongliang Tang, Rami Melhem (University of Pittsburgh), Adapting Processor Supply Voltage to Instruction-Level Parallelism, in the 2000 Kool Chips Workshop, held in conjuction with the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

A. Iyer and D. Marculescu (CMU), Run-time Scaling of Microarchitecture Resources in a Processor for Energy Savings, in the Kool Chips Workshop, held in conjuction with the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

H.-H. Lee, G. S. Tyson (University of Michigan), and M. Farrens (University of California, Davis), Eager Writeback - a Technique for Improving Bandwidth Utilization, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

K. M. Lepak, M. H. Lipasti (University of Wisconsin - Madison), Silent Stores for Free, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

Z. Zhang, Z. Zhu, X. Zhang (College of William and Mary), A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

T. Sherwood, S. Sair, B. Calder (University of California, San Diego), Predictor-Directed Stream Buffers, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

D. A. Jimenez, S. W. Keckler, C. Lin (University of Texas at Austin), The Impact of Delay on the Design of Branch Predictors, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

S. A. Vlaovic, E. S. Davidson, G. S. Tyson (University of Michigan), Improving BTB Performance in the Presence of DLLs, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

S. Chatterjee, C. Weaver, T. Austin (University of Michigan), Efficient Checker Processor Design, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

R. Canal, A. Gonzalez, J. E. Smith (University of Wisconsin - Madison), Very Low Power Pipelines using Significance Compression, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

A. Roth, G. S. Sohi (University of Wisconsin - Madison), Register Integration: A Simple and Efficient Implementation of Squash Re-Use, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

M. A. Postiff, D. A. Greene, T. N. Mudge (University of Michigan), The Store-Load Address Table and Speculative Register Promotion, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas (University of Rochester), Memory Hierarchy Reconfiguration For Energy And Performance In General-Purpose Processor Architectures, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

Z. Purser, K. Sundaramoorthy, E. Rotenberg (North Carolina State University), A Study of Slipstream Processors, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

T. H. Heil, J. E. Smith (University of Wisconsin - Madison), Relational Profiling: Enabling Thread Level Parallelism in Virtual Machines, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

S. J. Patel, T. Tung, S. Bose, M. Crum (University of Illinois at Urbana-Champaign), Increasing the Size of Atomic Instruction Blocks by using Control Flow Assertions, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

J.-M. Parcerisa, A. Gonzalez (Universitat Politecnica de Catalunya), Reducing Wire Delay Penalty through Value Prediction, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

E. Larson, T. Austin (University of Michigan), Compiler Controlled Value Prediction using Branch Predictor Based Confidence, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

A. Baniasadi (Northwestern University), A. Moshovos (University of Toronto), Instruction Distribution Heuristics for Quad-Clustered, Dynamically-Scheduled, Superscalar Processors, in the 33rd International Symposium on Microarchitecture (MICRO-33), December 2000.

D. Naishlos, J. Nuzman, C-W. Tseng, and U. Vishkin (University of Maryland), Evaluating multi-threading in the prototype XMT environment, in the 4th Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC-2000), held in conjunction with the 33rd Annual International Symposium on Microarchitecture (MICRO-33), December 2000.

Alvin Lebeck, Xiaobo Fan, Heng Zeng, and Carla Ellis (Duke University), Power Aware Page Allocation, in the ACM/IEEE 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX), Cambridge, MA, November 2000.

Jerome Burke, John McDonald, and Todd Austin (University of Michigan), Architectural Support for Fast Symmetric-Key Cryptography, in the ACM/IEEE 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX), Cambridge, MA, November 2000.

Karthik Sundaramoorthy, Zachary Purser, and Eric Rotenberg (North Carolina State University), Slipstream Processors: Improving both Performance and Fault Tolerance, in the ACM/IEEE 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX), Cambridge, MA, November 2000.

Vikram S.Adve, Rajive Bagrodia, James C.Browne, Ewa Deelman, Aditya Dube, Elias N.Houstis, John R.Rice, Rizos Sakellariou, David J.Sundaram-Stukel, Patricia J.Teller, and Mary K.Vernon, POEMS: End-to-End Performance Design of Large Parallel Adaptive Computational Systems, in IEEE Transactions on Software Engineering, Vol. 26, No. 11, November 2000.

J. Liang, S. Swaminathan, and R. Tessier (University of Massachusetts at Amherst), aSOC: A Scalable, Single-Chip Communications Architecture, in the 2000 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT-2000), October 2000.

Kevin Scott and Jack Davidson (University of Virginia), Exploring the Limits of Sub-word Level Parallelism, in the 2000 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT-2000), October 2000.

Jian Huang (Sun Microsystems) and David Lilja (University of Minnesota), Exploring Sub-block Value Reuse for Superscalar Processors, in the 2000 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT-2000), October 2000.

Gordon Bell, Kevin M. Lepak and Mikko H.Lipasti (University of Wisconsin), Characterization of Silent Stores, in the 2000 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT-2000), October 2000.

Sang-Jeong Lee (Soonchunhyang University, Korea) and Pen-Chung Yew (University of Minnesota), On Some Implementation Issues for Value Prediction on Wide-Issue Processors, in the 2000 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT-2000), October 2000.

Alex Ramirez, Josep L. Larriba-Pey and Mateo Valero (Universitat Politecnica de Catalunya, Spain), The Effect of Code Reordering on Branch Prediction, in the 2000 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT-2000), October 2000.

Kevin Skadron (University of Virginia), Margaret Martonosi and Douglas W. Clark (Princeton University), A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions, in the 2000 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT-2000), October 2000.

Timothy H. Heil and James E. Smith (University of Wisconsin, Madison), Concurrent Garbage Collection Using Hardware-Assisted Profiling, in the 2000 International Symposium on Memory Management (ISMM'00), October 2000.

Darko Stefanovic and Margaret Martonosi (Princeton University), Limits and Graph Structure of Available Instruction-Level Parallelism, in the 2000 European Conference on Parallel Computing (Euro-Par 2000), September 2000.

Carlos Navarro, Alex Ramírez, Josep-L. Larriba-Pey, and Mateo Valero (Universitat Polit`ecnica de Catalunya, Spain), On the Performance of Fetch Engines Running DSS Workloads, in the 2000 European Conference on Parallel Computing (Euro-Par 2000), September 2000.

Marian Stanca, Stamatis Vassiliadis, Sorin Cotofana, and Henk Corporaal (Delft University of Technology), Hashed Addressed Caches for Embedded Pointer Based Codes, in the 2000 European Conference on Parallel Computing (Euro-Par 2000), September 2000.

Kevin D. Rich and Matthew K. Farrens (University of California at Davis), The Decoupled-Style Prefetch Architecture, in the 2000 European Conference on Parallel Computing (Euro-Par 2000), September 2000.

AJ KleinOsowski, John Flynn, Nancy Meares, and David J. Lilja (University of Minnesota), Adapting the SPEC 2000 Benchmark Suite for Simulation-Based Computer Architecture Research, in the Workshop on Workload Characterization (WWC), held in conjunction with the International Conference on Computer Design (ICCD), September 2000.

Darko Stefanovic and Margaret Martonosi (Princeton University), On Availability of Bit-narrow Operations in General-purpose Applications, in the 10th International Conference on Field Programmable Logic and Applications (FPL 2000), August 2000.

Michael Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, and T. N. Vijaykumar (Purdue University), Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories, in the 2000 International Symposium on Low Power Electronics and Design (ISLPED-2000), July 2000.

Diana Marculescu (CMU), Profile-driven code execution for low power dissipation, in the 2000 International Symposium on Low Power Electronics and Design (ISLPED-2000), July 2000.

Kirk Cameron,  Empirical and Statistical Application Modeling Using On-Chip Performance Monitors, Ph.D. dissertation, Department of Computer Science, Illinois Institute of Technology, July 2000.

W. Ye, N. Vijaykrishna,, M. Kandemir, and M. J. Irwin (Penn State), The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool, in Design Automation Conference (DAC-2002), June 2000.

Mark Oskin, Frederic T. Chong, and Matthew Farrens (U.C. Davis), HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs, in the 27th Annual International Symposium on Computer Architecture (ISCA-2000), Vancouver, British Columbia, June 2000.

N. Vijaykrishnan, M. Kandemir, M.J. Irwin, H.S. Kim, and W. Ye (Penn State), Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower, in the 27th Annual International Symposium on Computer Architecture (ISCA-2000), Vancouver, British Columbia, June 2000.

Erik G. Hallnor and Steven K. Reinhardt (University of Michigan), A Fully Associative Software-Managed Cache Design,  in the 27th Annual International Symposium on Computer Architecture (ISCA-2000), Vancouver, British Columbia, June 2000.

Craig Zilles and Gurindar S. Sohi (University of Wisconsin), Understanding the Backward Slices of Performance Degrading Instructions, in the 27th Annual International Symposium on Computer Architecture (ISCA-2000), Vancouver, British Columbia, June 2000.

Kevin Lepak and Mikko Lipasti (University of Wisconsin), On the Value Locality of Store Instructions, in the 27th Annual International Symposium on Computer Architecture (ISCA-2000), Vancouver, British Columbia, June 2000.

Alex Zhi Ye, Andreas Moshovos, Scott Hauck, and Prithviraj Banerjee (Northwestern University), CHIMAERA: A high performance architecture with a tightly-coupled reconfigurable functional unit, in the 27th Annual International Symposium on Computer Architecture (ISCA-2000), Vancouver, British Columbia, June 2000.

Vikas Agarwal, M.S. Hrishikesh, Stephen Keckler, and Doug Burger (University of Texas at Austin), Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures, in the 27th Annual International Symposium on Computer Architecture (ISCA-2000), Vancouver, British Columbia, June 2000.

Brian Davis, Trevor Mudge (University of Michigan), Bruce Jacob, and Vinodh Cuppu (University of Maryland, College Park), DDR2 and low-latency variants, in the Proceedings of the Memory Wall Workshop, held in conjunction with the 27th International Symposium on Computer Architecture (ISCA-2000), June 2000.

S. Del-Pino, L. Piñuel, R. Moreno and F. Tirado (Universidad Complutense de Madrid, Spain), Value prediction as a cost-effective solution to improve embedded processor performance", in the 3th International Meeting on Vector and Parallel Processing (VECPAR'2000), June 2000.

Nirav H. Kapadia, Renato J. Figueiredo, and José A.B. Fortes (Purdue University), PUNCH: Web Portal for Running Tools, IEEE Micro, Vol. 20, No. 3, May/June 2000.

David Brooks and Margaret Martonosi (Princeton University), Value-Based Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance, in ACM Transactions on Computer Systems., Volume 18, No. 2, May 2000.

Xianfeng Zhou and Margaret Martonosi (Princeton University), Augmenting Modern Superscalar Architectures with Configurable Extended Instructions, in the 7th Reconfigurable Architectures Workshop (RAW 2000), held in conjunction with International Parallel & Distributed Processing Symposium (IPDPS 2000), May 2000.

Chengqiang Zhang and Sally A. McKee (University of Utah), Hardware-only stream prefetching and dynamic access ordering, in the Proceedings of the 14th International Conference on Supercomputing (ICS-2000), May 2000.

Chia-Lin Yang and Alvin R. Lebeck (Duke University), Push vs. pull: data movement for linked data structures, in the Proceedings of the 14th International Conference on Supercomputing (ICS-2000), May 2000.

Srinivas Mantripragada and Alexandru Nicolau (University of California, Irvine), Using profiling to reduce branch misprediction costs on a dynamically scheduled processor, in the Proceedings of the 14th International Conference on Supercomputing (ICS-2000), May 2000.

Ramon Canal and Antonio González (Universitat Polit~cnica de Catalunya, Spain), A low-complexity issue logic, in the Proceedings of the 14th International Conference on Supercomputing (ICS-2000), May 2000.

Y. Chung, K. Park, W. Hahn, N. Park, and V. K. Prasanna (University of California, Los Angeles), Performance of On-Chip Multiprocessors for Vision Tasks, in the 2000 International Parallel and Distributed Processing Symposium (IPDPS 2000), May 2000.

John Kalamatianos & David R. Kaeli (Northeastern University), Accurate Simulation and Evaluation of Code Reordering, in the 2000 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2000), Austin, Texas, April 2000.

Murali Annavaram, Gary S. Tyson and Edward S. Davidson (University of Michigan), Instruction Overhead and Data Locality Effects in Superscalar Processors, in the 2000 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2000), Austin, Texas, April 2000.

Lucian Codrescu (Georgia Institute of Technology), ATLAS: A Dynamically Parallelizing Chip-Multiprocessor for Gigascale Integration, Ph.D. Thesis, Electrical Engineering, Georgia Institute of Technology, April 2000.

Stephan Wong, Sorin Cotofana, and Stamatis Vassiliadis (Delft University of Technology), General-Purpose Processor Huffman Encoding Extension, in the Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC 2000), March 2000.

Z. Ye, N. Shenoy, and P. Banerjee (Northwestern University), A C Compiler for a Processor with a Reconfigurable Functional Unit, in the 2000 ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA-2000), February 2000.

Wayne A. Wong and Jean-Loup Baer (University of Washington), Modified LRU Policies for Improving Second-level Cache Behavior, in the 6th International Symposium on High-Performance Computer Architecture (HPCA-6), February 2000.

James Burns and Jean-Luc Gaudiot (University of California, Los Angeles), Quantifying the SMT Layout Overhead – Does SMT Pull Its Weight?, in the 6th International Symposium on High-Performance Computer Architecture (HPCA-6), February 2000.

Ramon Canal, Joan Manuel Parcerisa and Antonio González (Universitat Politècnica de Catalunya, Spain), Dynamic Cluster Assignment Mechanisms, in the 6th International Symposium on High-Performance Computer Architecture (HPCA-6), February 2000.

Ravi Rajwar, Alain Kagi, and James R. Goodman (University of Wisconsin, Madison), Improving the Throughput of Synchronization by Insertion of Delays, in the 6th International Symposium on High-Performance Computer Architecture (HPCA-6), February 2000.

Charles Lefurgy, Eva Piccininni, and Trevor Mudge (University of Michigan), Reducing Code Size with Run-time Decompression, in the 6th International Symposium on High-Performance Computer Architecture (HPCA-6), February 2000.

Sang-Jeong Lee (Soonchunhyang University, Korea), Yuan Wang, and Pen-Chung Yew (University of Minnesota), Decoupled Value Prediction on Trace Processors, in the 6th International Symposium on High-Performance Computer Architecture (HPCA-6), February 2000.

Michael Haungs, Phil Sallee, and Matthew Farrens (University of California, Davis), Branch Transition Rate: A New Metric for Improved Branch Classification Analysis, in the 6th International Symposium on High-Performance Computer Architecture (HPCA-6), February 2000.